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description the CXP87852/87860 is a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, pwm output, viss/vass circuit, 32khz timer/counter, remote control reception circuit, hsync counter, vsync separator and the measurement circuit which measures signals of capstan fg and drum fg/pg and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also the CXP87852/87860 provides sleep/stop functions which enable to lower power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation (4.5v to 5.5v) 122s at 32khz operation (2.7v to 5.5v) incorporated rom capacity 52k bytes (CXP87852), 60k bytes (cxp87860) incorporated ram capacity 2048 bytes peripheral functions ?a/d converter 8 bits, 12 channels, successive approximation system (conversion time of 20.0s at 16mhz) ?serial interface incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channel incorporated 8-bit and 8-stage fifo (auto transfer for 1 to 8 bytes), 1 channel incorporated two-wire 8-bit and 8-stage fifo (auto transfer for 1 to 8 bytes), 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32khz timer/counter ?high precision timing pattern generator ppg: maximum of 19 pins, 32 stages programmable rtg: 5 pins, 2 channels ?pwm/da gate output pwm: 12 bits, 2 channels (repetitive frequency of 62khz at 16mhz) da gate pulse output: 13 bits, 4 channels ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14 bits ?viss/vass circuit pulse duty auto detection circuit ?remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage fifo ?hsync counter 12-bit event counter (counts sync1 input.) interruption 23 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp piggyback/evaluator cxp87800 100-pin ceramic pqfp ?1 CXP87852/87860 e96215a16-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (piastic) structure silicon gate cmos ic
?2 CXP87852/87860 pbctl sck1 dpg so1 a a pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe1 pe2 to pe7 pf0 to pf3 pf4 to pf7 pg0 to pg7 pi1 to pi7 pj0 to pj7 v dd mp rst xtal extal clock generator/ system control ram 2048 bytes spc700 cpu core rom 52k/60k bytes interrupt controller 2 2 32khz timer/counter fifo frc capture unit programmable pattern generator ram 2 5 19 avss av ref av dd 2 a/d converter serial interface unit (ch0) ram 8 bit timer/counter 0 8 bit timer 1 vsync separator 14 bit pwm generator 12 bit pwm generator ch0 servo input control capstan drum ctl 2 3 2 12 bit pwm generator ch1 4 dab1 daa1 pwm1 dab0 daa0 pwm0 pwm rmc dfg cfg exi1 exi0 sync1 sync0 to/ddo ec si1 sck0 so0 si0 cs0 an0 to an11 realtime pulse generator int2 int0 int1/nmi 12 8 port a 8 port b 8 port c 8 port d 6 port e 4 4 port f 8 port g 8 port h 7 port i ph0 to ph7 tx tex a a prescaler/ time base timer viss/vass remocon input fifo serial interface unit (ch1) ch0 ch1 8 port j ppo0 to ppo18 rto3 to rto7 fifo hsync counter hcout 2 adj vss serial interface unit (ch2) fifo sda0 scl1 scl0 ckout sda1 2 2 block diagram
3 CXP87852/87860 pin assignment (top view) pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3/sda1 pd2/sda0 pd1/scl1 pd0/scl0 pi6/so1 pi7/si1 pe0/int0/ckout pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd v ss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 note) 1. nc (pin 90) is always connected to v dd . 2. vss (pins 41 and 88) are both connected to gnd. 3. mp (pin 39) is always connected to gnd.
4 CXP87852/87860 output/ real-time output output/ real-time output i/o/ real-time output i/o/ real-time output i/o input/input/output input/input/input/ output output/output output/output output/output output/output output/output output/output input input/input output/input i/o ouput input input (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits for upper 4 bits. can drive 12ma sink current. lower 4-bit output is n-ch open drain. (8 pins) (port e) 8-bit port. lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins) analog inputs to a/d converter. (12 pins) (port f) 8-bit port. lower 4 bits are for inputs; upper 4 bits are for outputs. lower 4 bits also serve as standby release input pin. (8 pins) serial clock (ch0) i/o. serial data (ch0) output. serial data (ch0) input. serial chip select (ch0) input. external event input for timer/counter. input to request external interruption. active at the falling edge. input to request external interruption. active at the falling edge. system clock frequency dividing output. pwm outputs. (2 pins) da gate pulse outputs. (4 pins) programmable pattern generator (ppg) output. functions as high precision real-time pulse output port. pb0 and pb2 can be 3-state controlled with ppg. (19 pins) real-time pulse generator (rtg) output. functions as high precision real-time pulse output port. pc3 can be 3-state controlled with rtg. (5 pins) symbol i/o description pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0/scl0 pd1/scl1 pd2/sda0 pd3/sda1 pd4 to pd7 pe0/int0/ ckout pe1/ec/int2/ hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 sck0 so0 si0 cs0 pin description coinsidence signal output of hsync counter. serial clock (ch2) i/o. (2 pins) serial data (ch2) i/o. (2 pins)
5 CXP87852/87860 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 ph0 to ph7 pi1/rmc pi2/pwm pi3/to/ ddo/adj pi4/int1/ nmi pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 extal xtal tex tx rst mp av dd av ref avss v dd nc vss input/input input/input input/input input/input input/input input/input input/input input/input output i/o/input i/o/output i/o/output/ output/output i/o/input/input i/o/i/o i/o/output i/o/input i/o input output input output input input input composite sync signal input. (2 pins) external input to frc capture unit. (2 pins) (port g) 8-bit input port. (8 pins) (port h) 8-bit output port. n -ch open drain output of me dium drive voltage (12v) and large current (12ma). (8 pins) remote control reception circuit input. 14-bit pwm output. timer/counter, ctl duty detection, 32khz oscillation adjustment output. input to request external interruption and non-maskable interruption. active at the falling edge. serial clock (ch1) i/o. serial data (ch1) output. serial data (ch1) input. (port i) 7-bit i/o port. i/o port can be set in a unit of single bits. (7 pins) (port j) 8-bit i/o port. i/o and standby release input function can be set in a unit of single bits. connects a crystal oscillator for system clock. when supplying the external clock, input the external clock to extal and input the opposite phase clock to xtal . connects a crystal oscillator for 32khz timer/counter clock. the 32khz crystal oscillator is inserted between tex and tx. when used as event counter, connect the clock source to tex and leave tx open. system reset; active at low level. test mode input. always connect to gnd. positive power supply of a/d converter. reference voltage input of a/d converter. gnd of a/d converter. positive power supply. connect v dd pin to v dd . no connected. connect to v dd in normal operation. gnd. connect both vss pins to gnd. symbol i/o description capstan fg input. drum fg input. drum pg input. playback ctl pulse input. external event input for timer/counter.
6 CXP87852/87860 aaaa aa ppo8, ppo10 data data bus pb0, pb2 data rd (port b) aa ppo9, ppo11 data data bus rd (port b) aaaaa a aaa a aaaaa ppg control status register bit 0 3-state control selection ppo9, ppo11 data output becomes active from high impedance by data writing to port register. output becomes active from high impedance by data writing to port register. aaaa aaaa pb1, pb3 data 12 pins 2 pins 2 pins hi-z hi-z when reset pa0 /ppo0 to pa7/ppo7 pb4/ppo12 to pb7/ppo15 pb0/ppo8 pb2/ppo10 hi-z pb1/ppo9 pb3/ppo11 aaaa aa ppo data data bus output becomes active from high impedance by data writing to port register. port a, port b data rd (port a or port b) input/output circuit formats for pins port a port b pin circuit format
7 CXP87852/87860 rto3 data data bus rd (port c) aaa aaa pc3 direction aaa aaa pc3 data aa aa rto4 data aaaaa a aaa a aaaaa rtg interruption control register bit 7 3-state control selection data bus rd (portc) aaa pc4 direction aaa aaa pc4 data aa aa rto data is or-gate data of ch0 and ch1. a a ip a a ip rto4 data 0 when reset 0 when reset 6 pins hi-z hi-z pc0/ppo16 to pc2/ppo18 pc5/rto5 to pc7/rto7 pc3/rto3 hi-z pc4/rto4 ppo, rto data data bus rd (port c) aaa aaa aa aa port c direction aaa aaa port c data input protection circuit ip aa aa 0 when reset port c when reset pin circuit format 1 pin 1 pin
8 CXP87852/87860 data bus rd (port d) aaaa aa port d direction aaaa aaaa port d data ip aa aa 0 when reset ? ? large current 12ma 4 pins hi-z hi-z pd0/scl0 pd1/scl1 pd2/sda0 pd3/sda1 pd4 to pd7 hi-z scl, sda aa aa aa aa ip aaaa aaaa port d data serial interface ch2 output enable data bus rd (port d) to another serial ch2 pin scl, sda (serial ch2 circuit) ? ? large current 12ma bus sw schmitt input port d port d pe0/int0/ ckout 1 pin data bus rd (port e) a a esl0 ip aa aa aaa aaa aaa mpx interruption circuit ps1 ps2 ps3 01 10 11 esl1 port e selection port e when reset pin circuit format 4 pins
9 CXP87852/87860 hi-z pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 4 pins 2 pins hi-z high level pe6/dab0 pe7/dab1 data bus rd (port e) aaaa aaaa aa aa aaa a a a a a a aaa da gate output hi-z control mpx aaaa aaaa port e data port/da output selection 1 when reset data bus rd (port e) aaaa aaaa aa aa aaa a a a a a a aaa da gate output, pwm output hi-z control mpx aaaa aaaa port e data port/da output selection 0 when reset an0 to an3 aa aa a a ip a/d converter input multiplexer 4 pins port e when reset pin circuit format port e hi-z pe1/ec/int2 /hcout 1 pin data bus rd (port e) a a ip aa aa interruption circuit/ event counter from hsync counter hi-z control hcout port e
10 CXP87852/87860 4 pins hi-z pf4/an8 to pf7/an11 a/d converter data bus rd (port f) aaaa aaaa a a port/ad selection ip aa aa aaaa port f data input multiplexer 0 when reset port f 8 pins hi-z pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 aa aa a a ip rd (port g) data bus schmitt input servo input note) for pg4/sync0, pg5/sync1, cmos schmitt input and ttl schmitt input can be selected with the mask option. port g 8 pins hi-z ph0 to ph7 data bus rd (port h) aa aa aaaa aaaa port h data ? large current 12ma medium drive voltage 12v ? port h when reset pin circuit format rd (port f) data bus aa aa a a ip input multiplexer a/d converter 4 pins hi-z pf0/an4 to pf3/an7 port f
11 CXP87852/87860 3 pins hi-z hi-z pi1/rmc pi4/int1/nmi pi7/si1 pi5/sck1 pi6/so1 2 pins 8 pins hi-z pj0 to pj7 aa aa standby release aaaa aaaa port j data aa aa ip data bus rd (portj) aaaa aaaa port j direction aa aa edge detection data bus rd (port j direction) 0 when reset aa aa aaa a a a a a a aaa mpx aaaa port i data aa ip data bus rd (port i) aaaa port i direction aaaa aaaa port i function selection aa aa aa mpx serial interface ch1 serial interface ch1 0 when reset pi6 is not schmitt input. aa aa pi1...remote control circuit pi4...interruption circuit pi7...serial interface ch1 aaaa aaaa port i data aa aa ip data bus rd (port i) aaaa aaaa port i direction schmitt input 0 when reset port j port i port i when reset pin circuit format 2 pins hi-z pi2/pwm pi3/to/ ddo/adj aa aa aaa a a a a a a aaa pi2...14-bit pwm pi3...timer/counter, ctl duty detection circuit, 32khz timer mpx aaaa aaaa port i data aa aa ip data bus rd (port i) aaaa aaaa port i direction aaa a a a aaa port i function selection 0 when reset 0 when reset port i
12 CXP87852/87860 2 pins oscillation extal xtal aa aa aa aa ip aa aa extal xtal shows the circuit composition during oscillation. feedback resistor is removed during stop mode. xtal becomes high level. 2 pins oscillation tex tx aa aa ip aa aa tex tx shows the circuit composition during oscillation. feedback resistor is removed during 32khz oscillation circuit stop by software. at this time tex pin outputs low level and tx pin outputs high level. 32khz timer/counter 1 pin hi-z sck0 sck0 output enable aa internal serial clock from sio a ip schmitt input external serial clock to sio 1 pin low level rst aa aa aa aa ip schmitt input pull-up resistor mask option op when reset pin circuit format so0 output enable a a so0 from sio 1 pin hi-z hi-z cs0 si0 aa aa aa aa ip schmitt input sio 2 pins so0
13 CXP87852/87860 ? 1 av dd should not exceed v dd + 0.3v. ? 2 v in and v out should not exceed v dd + 0.3v. ? 3 the large current drive transistors are the n-ch transistors of the port d (pd) and port h (ph). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d low level output current 0.3 to +7.0 avss to +7.0 ? 1 0.3 to +0.3 0.3 to +7.0 ? 2 0.3 to +7.0 ? 2 0.3 to +15.0 5 50 15 20 130 20 to +75 55 to +150 600 v v v v v v ma ma ma ma ma c c mw port h pin total of output pins ports excluding large current output (value per pin) large current output port (value per pin ? 3 ) total of output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
14 CXP87852/87860 analog supply voltage high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 v dd v dd 5.5 5.5 v dd + 0.3 0.3v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 2.0 4.5 0.7v dd 0.8v dd 2.2 v dd 0.4 0 0 0 0.3 20 av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing modes guaranteed operation range for 1/16 frequency dividing mode or during sleep mode guaranteed operation range by tex clock guaranteed data hold range during stop mode ? 1 includes the serial ch2 input ? 2 cmos schmitt input ? 3 and pe0/int0 pin cmos schmitt input ? 7 ttl schmitt input ? 4 extal pin ? 5 and tex pin ? 6 includes the serial ch2 input ? 2 cmos schmitt input ? 3 and pe0/int0 pin ttl schmitt input ? 4 extal pin ? 5 and tex pin ? 6 v dd ? 1 av dd and v dd should be set to the same voltage. ? 2 normal input port (pc, pd4 to pd7, pf0 to pf3, pg, pi and pj), mp pin ? 3 sck0, rst, ec/int2, rmc, int1/nmi, sck1 and si1 ? 4 pg4 and pg5 (when ttl schmitt input is selected with mask option) ? 5 specifies only when the external clock is input. ? 6 specifies only when the external event count clock is input. ? 7 cs0, si0, and pg (for pg4 and pg5, when cmos schmitt input is selected with mask option.) recommended operating conditions (vss = 0v reference)
15 CXP87852/87860 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 6.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 0.5 0.1 0.1 1.5 v v v v v v v a a a a a a a a ? pd, ph pa to pc, pd4 to pd7, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst ? 1 item symbol pins conditions min. i iz i loh rbs v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 0.4 0.6 40 40 10 10 400 10 50 10 120 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = 20 to +75 c, vss = 0v reference) v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v v oh = 12v v dd = 5.5v v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v i/o leakage current open drain output leakage current (in n-ch tr off state) serial interface ch2 bus switch connection impedance (in output tr off state) pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst ? 1 ph pd0 to pd3 scl0: scl1 sda0: sda1 pd0 to pd3 (scl0, csl1 sda0, sda1)
16 CXP87852/87860 item symbol pins conditions min. pc, pd, pe0, pe1, pf, pg, pi1 to pi7, pj, cs0, si0, sck0, an0 to an3, extal, xtal, tex, tx, mp, rst clock 1mhz 0v other than the measured pins v dd i dd1 i dds1 i dd2 i dds2 i dds3 c in typ. max. unit v dd = 5v 0.5v sleep mode v dd = 5v 0.5v v dd = 5v 0.5v supply current ? 2 input capacity high-speed mode (1/2 frequency dividing clock) operation stop mode ( extal and tex pins oscillation stop) 33 2.5 56 10 10 50 8 110 35 10 20 ma ma a a a pf v dd = 3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf) ? 1 for rst pin, specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ? 2 when all output pins are open.
17 CXP87852/87860 fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) fig. 1, fig. 2 (external clock drive) fig. 3 fig. 3 fig. 2 v dd = 2.7 to 5.5v (32khz clock applied condition) fig. 3 fig. 3 ? 1 t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa external clock extal xtal 74hc04 aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 aaaaa a aaa a aaaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ns khz s ms item symbol pins conditions unit min. typ. 1 28 4 t sys ? 1 10 32.768 max. 16 200 20 20 (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing fig. 2. clock applied condition tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
18 CXP87852/87860 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) the load of sck output mode and so output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width sck cycle time sck high and low level widths si input setup time (for sck ) si input hold time (for sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit condition
19 CXP87852/87860 fig. 4. serial transfer timing (ch0) cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
20 CXP87852/87860 serial transfer (ch1) (sio mode) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input setup time (for sck1 ) si1 input hold time (for sck1 ) sck1 so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 16000/fc t sys +100 8000/fc 50 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing (sio mode) sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
21 CXP87852/87860 so1 cycle time si1 data setup time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 ? 1 2 2 104 s s s item symbol pin condition min. typ. max. unit serial transfer (ch1) (special mode) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) ? 1 t lcy is specified only when serial mode register (ch1) (siom1: 05fz h ) lower 2 bits (so1 clock selection) are set at 104s. note) the load of so1 pin is 50pf + 1ttl. fig. 6. serial transfer ch1 timing (special mode) so1 si1 t lcy start bit output data bit t lcy 0.5v dd 0.8v dd 0.2v dd t lcy/2 t lsu t lhd input data bit
22 CXP87852/87860 serial transfer (ch2) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repeated transfers data hold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 2.6 1.0 1.0 1.0 1.0 0 ? 1 100 1.6 400 300 300 khz s s s s s s ns ns ns s symbol pin condition min. max. unit ? 1 the scl fall time (300ns max.) is not included in the data hold time. fig. 7. serial transfer timing (ch2) p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 8. device recommended circuit device device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor (r p ) must be connected to sda0 (or sda1) and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 ? or less) can be used to reduce the spike noise caused by crt flashover.
23 CXP87852/87860 external clock input frequency external clock input pulse width external clock input rise and fall times hcout output delay time (for sync ) hcout output rise and fall times f hck t wh , t wl t r , t f t hlh , t hhl t tlh t thl sync1 sync1 sync1 hcout hcout external clock input sync1 t r = t f = 6ns external clock input sync1 t r = t f = 6ns 33 12 200 t sys + 220 50 25 mhz ns ns ns ns ns item symbol pin condition min. typ. max. unit (3) hsync counter note1) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ). note2) the load of hcout pin is 50pf. (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 1/f hck t f t wh 0.8v dd t r t wl 0.5v dd 0.2v dd t hlh 0.8v dd 0.5v dd 0.2v dd t tlh t thl t hhl sync1 hcout fig. 9. hsync counter timing
24 CXP87852/87860 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i refs s s v v av dd av ref 1.0 ma 10 a 0.6 160/f adc ? 1 12/f adc ? 1 av dd 0.5 0 item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (ta = 20 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) 8 1 2 lsb lsb analog input linearity error 00 h 01 h fe h ff h digital conversion value fig. 10. definitions of a/d converter terms an0 to an11 av ref ? 1 f adc indicates the below values due to the peripheral clock control register (pcc: 05f8 h ) bit 3 and clock control register (clc: 00fe h ) upper 2 bits. pcc bit 3 clc upper 2 bits 00 ( = f ex /2) 01 ( = f ex /4) 11 ( = f ex /16) f adc = fc/2 f adc = fc/4 f adc = fc/16 f adc = fc f adc = fc/2 f adc = fc/8 0 ( /2 selection) 1 ( selection)
25 CXP87852/87860 external interruption high and low level widths reset input low level width int0 int1 int2 nmi pj0 to pj7 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (5) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 nmi pj0 to pj7 (during standby release input) (falling edge) fig. 11. interruption input timing t rsl 0.2v dd rst fig. 12. reset input timing (6) others (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cfg input high and low level widths dfg input high and low level widths dpg minimum pulse width dpg minimum removal time pbctl input high and low level widths exi input high and low level widths t cfh t cfl t dfh t dfl t dpw t rem t cth t ctl t eih t eil cfg dfg dpg dpg pbctl exi0 exi1 ns ns ns ns ns ns symbol pins min. 24 t frc + 200 16 t frc + 200 8 t frc + 200 16 t frc + 200 8 t frc + 200 + t sys 8 t frc + 200 + t sys max. unit t sys = 2000/fc t sys = 2000/fc conditions note 1) t frc = 1000/fc [ns] note 2) t sys indicates three values according to the contents of the clock control register (clc: 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 )
26 CXP87852/87860 0.8v dd cfg t cfh t cfl 0.2v dd 0.8v dd dfg t dfh t dfl 0.2v dd 0.8v dd pbctl t cth t ctl 0.2v dd 0.8v dd exi0 exi1 t eih t eil 0.2v dd 0.8v dd t dpw t rem dpg t rem fig. 13. other timings
27 CXP87852/87860 appendix fig. 14. recommended oscillation circuit aaaa a aa a aaaa extal xtal c 1 c 2 rd (i) aaaa a aa a aaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 30 18 470k (ii) 32.768khz 10 5 16 (12) 10 16.00 5 16 (12) 16 (12) 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (i) ? 1 the input circuit format can be selected for pg4/sync0 and pg5/sync1, respectively. item content reset pin pull-up resistor input circuit format ? 1 non-existent c-mos schmitt existent ttl schmitt mask option table 16.00 12 12 16 (12)
28 CXP87852/87860 characteristics curve i dd vs. v dd (fc = 16mhz, ta = 25 c, typical) 1/4 dividing mode 32khz sleep mode sleep mode 1/16 dividing mode 1/2 dividing mode 32khz mode (instruction) v dd supply voltage [v] 3.0 4.0 5.0 6.0 2.5 i dd supply current [ma] 0.1 0.01 (10a) 1 10 i dd vs. fc (v dd = 5.0v, ta = 25 c, typical) 51015 0 20 fc system clock [mhz] 1/4 dividing mode sleep mode i dd supply current [ma] 40 3.5 4.5 5.5 10 30 1/2 dividing mode 1/16 dividing mode 0
29 CXP87852/87860 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead specifications item lead material copper alloy lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony corporation

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